Projection display systems are a common component in home theater and digital cinema applications. Projection display system need achieve only a level of brightness appropriate to the size of the screen and the position of the audience in order to be useful, whereas a direct view display must be physically large enough. Size, cost, brightness, contrast and resolution are all important characteristics for projection displays. Most recently digital cinema projectors utilizing typically three reflective mode spatial light modulators have been fielded in significant numbers. These digital cinema systems utilize high power light sources such as xenon lamps and are able to project images onto screens that may be 90 feet or more wide. In 2010 the Eastman Kodak Company demonstrated a digital cinema projection system prototype system utilizing high power lasers as an alternative to projection systems utilizing xenon lamps for illumination.
A projection system for such applications must meet a number of performance requirements to provide a satisfactory viewing experience for an audience drawn from the general public. The displayed images must not exhibit objectionable flicker or motion blurring due to an unacceptably low data frame rate or any other cause. The displayed images should not exhibit choppy motion due to a low data capture rate during development of the material being shown. The projection system must reproduce colors such that the images on the screen appear true to life.
Methods for dealing with these issues are well known in the art. Flicker is well understood. In film based cinema images are captured at a rate of 24 frames per second. Film projectors use a double blade shutter so a given frame is shown twice after being pulled down into the display position, thus raising the effective rate of display to 48 frames per second. Early experimental television display systems based on CRTs were configured to match this frame rate but it proved ineffective at eliminating flicker because of differences in the stability of the displayed images, but this was largely overcome when the frame rate was raised to 60 frames per second. Motion blurring was alleviated by the double shutter method although the cause differs from that of flicker. Motion blurring was largely not present in CRT based displays because the phosphors in the CRT had low persistence, resulting in images comprising a set of impulses of light that are a millisecond or two long within a frame of over 16 milliseconds duration. Solutions to blurring in hold type displays such as liquid crystal displays were identified in “Modified drive method for OCB LCD”, Proceeding of the International Display Research Conference, 1997, by H. Nakamura et al. The authors describe therein the backlight to a direct view transmissive display was periodically blanked electronically. The duration of the blanking period and the best rate for blanking were determined experimentally. Later evidence suggests that each display type may require a different optimal duration.
Scrolling color projection displays comprise a part of the art of liquid crystal displays. Previously, a rear projection television product incorporating a scrolling color display subsystem was offered for sale. The general operating principle of a scrolling color display system is that illuminating light in the form of three primary color bands with dark guard bands between them is formed. These bands are substantially the width of the display horizontally and relatively narrow vertically. By convention the rows of a display run horizontally and the columns of a display run vertically. Scanning optics cause the colored bands to be sequentially scanned down the face of a spatial light modulator, such as a liquid crystal on silicon microdisplay. At substantially the same time that each color passes over a given row on the spatial light modulator that row is addressed with the first of a series of pulse width modulation data values appropriate to that row and that color, with the duration of the sequence of pulses substantially contemporaneous with the duration of the illumination of that row by that color, thereby creating that color portion of that row on the display. The image is projected by a projection lens onto a viewing surface, such as a screen. The data for a given color for a row may be displayed across a number of consecutive illuminations of that row by that color.
In this application the terms microdisplay, spatial light modulator, imager and panel are all understood to refer to a device capable of modulating light in order to generate images. The microdisplay may be a reflective or transmissive liquid crystal device, a MEMS device, or another type device based on other modulation principles.
The operation of the illumination optics in a scrolling color projection system is disclosed in U.S. Pat. No. 5,548,347, Melnik, et al, assigned to Philips, the contents whereof being incorporated into this application by reference. Note particularly FIG. 16. The phase difference between the three rotating prism demonstrates clearly how multiple color stripes can be made to illuminate a single display.
An alternative implementation of a scrolling color illumination system is disclosed in U.S. Pat. No. 5,845,981, Bradley, assigned to Philips, the contents whereof being incorporated into this application by reference in its entirety. FIG. 1 discloses scrolling color projection system wherein three separate light sources illuminate a single reflective mode spatial light modulator through a polarizing beam splitter.
FIG. 1 presents a scrolling color projection system 105 based in part on Bradley. The example depicts a scrolling color projection system comprising three light sources 110R (red), 110G (green) and 110B (blue) oriented such that the illumination beams 115R, 115G and 115B are not parallel. The angle between 110R and 110G is equal to the angle between 110G and 110B. All three beams of light enter hexagonal rotating prism 120 and are refracted according to Snell's Law. As the three beams exit the rotating prism they are again refracted according to Snell's Law. Collimating lenses 130 and 140 receive the non-parallel output of rotating prism 120 and collimate the light so that it enters polarizing beam splitter 150. The polarizing beam splitter would most typically be one based on the principles set forth in U.S. Pat. No. 2,403,731, MacNeille, “Beam Splitter” and may incorporate many of the later improvements to the thin film stack forming the multilayer film within a MacNeille and to the transparent optical material from which a MacNeille PBS components are formed. S-polarized light is reflected by PBS 150 while p-polarized light passes through PBS 150 and is thereafter not used. Reflected beams 115R, 115G, and 115B are as a result polarized when they encounter spatial light modulator (SLM or microdisplay) 160. Optional spatial light modulator 165 is deployed on a second port of PBS 150. Microdisplay 165 is illuminated by the aforementioned p-polarized light (not shown). Light reflect by microdisplay 165 in its on state is s-polarized and therefore reflected by PBS 150. Stereoscopic images may be placed on microdisplay 160 and optional microdisplay 165 as is well known in the art. In this example the spatial light modulator is a reflective mode liquid crystal on silicon microdisplay. Responsive to a drive voltage supplied by external circuitry (not shown), the liquid crystal layer in the SLM modifies the polarization state of the light passing through the liquid crystal layer. Light reflected by spatial light modulator 160 that is now partially or completely p-polarized will pass through PBS 150 to lens group 170 that will project it onto a viewing screen.
FIG. 2 presents an instantaneous view of the arrangement of color bands and dark guard bands on the face of spatial light modulator 180. Red color band 184 and green color band 188 are separated by dark guard band 186. Green color band 188 and blue color band 192 are separate by dark guard band 190. Blue color band 192, near the bottom of the face of spatial light modulator 180 and red color band 184 are separate by dark guard band 182. Note that dark guard band 182 is present at both the top and the bottom of the face of spatial light modulator 180. This is a necessary consequence of the scrolling of the color across the face of spatial light modulator 180. Arrow 194 indicates the direction in which color bands 184, 188 and 192 and dark guard bands 182, 195 and 192 move across the face of spatial light modulator 180 as a function of time. The a color band passes the bottom of the face of spatial light modulator 180 it begins to appear simultaneously at the top and the bottom of spatial light modulator 180.
Because the writing of data to a row of the panel must be synchronized with the illumination of that row with the proper color, it is necessary to maintain a phase relationship between the rotation of the prisms and the writing of data so that each color band and the data for that color band are synchronized. U.S. Pat. No. 6,690,432, Janssen, et al, assigned to Philips, the contents whereof are incorporated by reference into this application, discloses a method for achieving and maintaining alignment between the display data and the phase position of a rotating prism.
Other means for establishing scrolling color illumination are known in the art. See, for example, U.S. Pat. No. 7,066,605, Dewald, et al, for an example based on a color wheel with the color segments arranged in a spiral. The contents of U.S. Pat. No. 7,066,605 are incorporated into this application by reference.
The microdisplay used in the Philips product is disclosed in “An Improved WXGA LCOS Imager for Single Panel Systems”, Willem Sloof, et al, Proceedings of the Asia Symposium on Information Display 2004, pages 150-153, hereinafter referred to as the Sloof paper. The text of the Sloof paper states that the display creates gray scale by the application of one of 256 voltages provided by a global voltage reference source and that the method of selecting the voltage is a digital comparator circuit. It further states that the display only writes data to a row once just prior to the arrival of a color band at that row and that the row is reset by draining the charge just prior to the writing of fresh data immediately prior to the arrival of a subsequent color band This device hereinafter is referred to as the “Sloof microdisplay”. The contents of this paper are incorporated by reference herein in its entirety into this application.
In U.S. Pat. No. 8,421,828 and its continuation, pending U.S. patent application Ser. No. 13/790,120, Hudson, et al, (hereinafter '120) disclose a method for applying pulse width modulation to a digital display backplane. The modulation method uses different row spacings within a group of row write actions to form a template that can then be repeated by adjusting the start point of a subsequent application of the template while maintaining the same row spacing between members of the group of said row write actions. Normally the offset is one row although it may be a different number of rows. The offset between the rows and the number of rows forming the template determines the duration of one least significant bit (lsb) based on a constant time required to write each row of data. U.S. patent application Ser. No. 13/790,120 is a parent to the present application.
A microdisplay capable of being pulse width modulated according to the method of the above patent application is disclosed in U.S. Pat. Nos. 7,443,374 and 7,468,717, both Hudson, and in U.S. Pat. No. 8,040,311, Hudson et al, hereinafter collectively “Hudson microdisplay”. The Hudson patents disclose a family of backplanes with a number of common characteristics described below. The contents of these patents are incorporated herein by reference.
The Hudson microdisplays resemble the Sloof microdisplay in that each Hudson patent discloses a microdisplay backplane wherein the rows are addressed through a row decoder scheme such that the rows need not be written in sequential order as is the case with a shift register method of delivering data to rows of a display.
The Hudson microdisplays differ from the Sloof microdisplay in two important respects. The backplanes of the Hudson microdisplays enable pure binary modulation of the liquid crystal. Only two voltages are available to be applied to the pixel mirrors and gray scale is generated by duty cycle modulation. DC balance of the Hudson microdisplays takes place independently of the writing of data to the backplane through a control element within the pixel circuit coordinated with external modulation of the counter electrode voltage. In the Sloof microdisplay the drive of the microdisplay backplane is analog in that up to 256 discreet voltages may be stored on a capacitor within the pixel drive circuit to be asserted onto the pixel mirror. One consequence is that DC balance takes place on consecutive loads of the backplane as is described in the Sloof paper at page 153, left hand column, first full paragraph.
FIGS. 3 and 4 show the general construction of a liquid crystal on silicon (LCOS) microdisplay panel 200. A single pixel cell 205 includes a liquid crystal layer 230 between a transparent common electrode 242 formed on glass substrate 240, and a pixel electrode 250. Alignment layers (not shown) of a suitable material such as polyimide or silicon dioxide (SiO2) as is well known in the art, are interposed between transparent electrode 242 and liquid crystal layer 230 and between liquid crystal layer 230 and pixel electrode 250. A storage element 210 is coupled to the pixel electrode 250, and includes complementary data input terminals 212 and 214, a data output terminal 216, and a control terminal 218. The storage element 210 is responsive to a write signal placed on control terminal 218, reads complementary data signals asserted on a pair of bit lines (BPOS and BNEG) 220 and 222, and latch the data signal through the output terminal 216. Since the output terminal 216 is coupled to the pixel electrode 250, the data (i.e. high or low voltage) passed by the storage element 210 is imparted on pixel electrode 250. Pixel electrode 250 is preferably formed from a highly reflective polished aluminum. In the LCD display panel in accordance with the present invention, a pixel electrode 250 is provided for each pixel in the display. For example, in a Full High Definition display system conforming to the SMPTE 274M-2005 standard that requires an array of 1920×1080 pixels, there would be an individual pixel electrode 250 for each of the 2,073,600 pixels in the array. Transparent common electrode 242 is preferably formed from Indium Tin-Oxide (ITO) on glass substrate 240 by some suitable process such as sputtering. A voltage (VITO) is applied to transparent common electrode 242 through a common electrode terminal (not shown) and in conjunction with the voltage applied to each individual pixel electrode, determines the magnitude and polarity of the voltage across liquid crystal layer 230 within each pixel cell 205 in the display 200.
When incident polarized beam of light 260 is directed at pixel cell 205, passes through transparent common electrode 242 the polarization state of incident beam of light 260 is modified by the liquid crystal material 230. The manner in which the liquid crystal material 230 modifies the state of polarization of incident beam of light 260 is dependent on the orientation of the liquid crystal molecules within the path of the beam of light 260 which is in turn dependent on the RMS voltage applied across the liquid crystal between common electrode 242 and pixel electrode 250. For example, applying a certain voltage across the liquid crystal material 230 will reflect beam of light 262 but in a form wherein the polarization state of beam of light 262 is only identical to that of beam of light 260 when the molecules of liquid crystal layer 230 are oriented such that no change to the polarization state of beam of light 260 occurs. This is well known in the art. When reflected beam of light 262 possesses a polarization state differing from that of incident beam of light 260, thus encoding information onto the beam of light 262.a fraction of the incident polarized light to be reflected back through the liquid crystal material and the transparent common electrode 240 in a modified polarization state that will pass through subsequent polarizing elements. After passing through the liquid crystal material 230, the incident light beam 260 is reflected by the pixel electrode 250 and back through the liquid crystal material 230. After reflected beam of light 262 passes through subsequent polarizing elements and is thereby analyzed, according to the term of art, the analyzed beam of light (not shown) is attenuated according to the specifics of the exact polarization state of reflected beam of light 262. A specific example of a polarizing element is found at element 150, FIG. 1. The intensity of exiting light beam 262 is thus dependent on the degree of polarization rotation imparted by the liquid crystal material 230, which is in turn dependent on the voltage applied across the liquid crystal material 230.
Storage element 210 is preferably formed from a CMOS transistor array in the form of an SRAM memory cell, i.e., a latch, but may be formed from other known memory logic circuits. SRAM latches are well known in semiconductor design and manufacturing and provide the ability to store a data value, as long as power is applied to the circuit. Other control transistors may be incorporated into the memory chip as well. The physical size of a liquid crystal display panel utilizing pixel cells 205 is largely determined by the resolution capabilities of the device itself as well as industry standard image sizes. For example, a Full High Definition (FHD) system that requires a resolution of 1920×1080 pixels requires an array of storage elements 210 and a corresponding array of pixels electrodes 250 that are 1920 columns wide by 1080 rows high (i.e. 2,073,600 pixels). An HD (high definition) display system that requires a resolution of 1280×720 pixels, requires an array of storage elements 210 and a corresponding array of pixels electrodes 250 that are 1280 long by 720 wide (i.e. 921, 600 pixels). Various other display standards may be supported by a display in accordance with the present invention, including XGA (1024×768 pixels), UXGA (1600×1200 pixels), and various wide screen formats (2000×1000 pixels). Any combination of horizontal and vertical pixel resolution is possible. The precise configuration is determined by industry applications and standards or by the ingenuity of individual developers. For example, the company Red.com—a manufacturer of camera for digital cinema—has released a Red One digital recording camera with a native resolution of 4096 by 2308, a 16:9 aspect ratio similar to the HDTV formats, and the Victor Corporation of Japan (JVC) has released for sale a projection system with a native resolution of 4096 by 2400, it is only possible to presume that additional ultra-high resolution products will emerge with varying numbers of rows and columns. None of these possibilities fall outside the scope envisioned for the present application.
Since the transparent common electrode 242 and glass substrate 240 form a single common electrode, their physical size will substantially match the total physical size of the pixel cell array with some margins to permit external electrical contact with the ITO and space for gaskets and a fill hole (not shown) to permit the device to be sealed after it is filled with liquid crystal.
In U.S. Pat. No. 8,421,828, an inventor of the present invention discloses a method for applying pulse width modulation to a digital display backplane. The modulation method uses different row spacings within a group of row write actions to form a template that can then be repeated by adjusting the start point of a subsequent application of the template while maintaining the same row spacing between members of the group. Because the row write actions are not always physically adjacent it is necessary to insure that the rows of the display are addressed using row address decoder means and not using a shift register write mechanism. A suitable row addressing scheme has long been known in the art of digital memory devices, including SRAM memories. A suitable implementation of a row address decoder circuit is disclosed in “Modern MOS Technology: Processes, Devices, and Design”, pp. 208-211, DeWitt G. Ong, McGraw-Hill, 1984.
FIG. 5 shows an electro-optical curve (EO-curve or liquid crystal response curve) for a typical liquid crystal mode known as a 63.6° mixed-mode-twisted-nematic (MTN) with optical compensation operated in the normally white (NW) mode from Robinson et al, “Polarization Engineering for LCD Projection”, page 123. Three curves are presented for three different wavelengths of light. MTN modes are often cited as optimal for field sequential color applications because of their low drive voltages, relatively high efficiency and the availability of device configurations allow the use of a single dark state voltage and a single bright state voltage for all colors. As illustrated in FIG. 5, as the voltage applied to the liquid crystal increases, the degree of rotation that is induced onto the polarization state of the reflected light is decreased. Liquid crystal material 130 (FIG. 4) has an RMS voltage VSAT, where its degree of polarization rotation is at a maximum (white display) and an RMS voltage VTT where the polarization rotation is at a minimum (black display). Within the range between VTT and VSAT, as the RMS voltage increases; the brightness of the light that is transmitted through liquid crystal material 130 (FIG. 4) will decrease from a brighter state to a darker state. At an RMS voltage that corresponds to the point of 100% brightness, the liquid crystal components are aligned substantially in a fan of liquid crystal molecules, thus allowing the light to completely pass through and reflected by the pixel electrode 150. At an RMS voltage that corresponds to the point of 0% brightness, the crystal components are aligned in a vertical stack of liquid crystal molecules such that the polarization of the reflected light is substantially identical to that of the incoming light source, thus preventing the light from passing through the polarizing element for display. The useful portion of the EO curve is voltage range between VTT and VSAT.
A useful feature of a liquid crystal cell with spectral performance features such as that of FIG. 5 is that the slope of the electro-optic curve is relatively uniform over the wavelength range of interest.
FIG. 6 shows a block diagram of single pixel cell 305 of a display compatible with the modulation method of the present invention after the pixel circuit disclosed in U.S. Pat. No. 7,443,374. Pixel cell 305 comprises storage element 300, DC balance control element 320, and inverter 340. DC balance control element 320 is preferably a CMOS based logic device that can selectively pass to another device one of several input voltages. Storage element 300 comprises complementary input terminals 302 and 304, respectively coupled to data lines (BPOS) 350 and (BNEG) 352. Storage element 300 also comprises complementary enable terminals 306 and 307 coupled to word line (WLINE) 356, and a pair of complementary data output terminals (SPOS) 308, and (SNEG) 310. In the present embodiment, storage element 300 is an SRAM latch, but those skilled in the art will understand that any storage element capable of receiving a data bit, storing the bit, and asserting the complementary states of the stored bit on complementary output terminals may be substituted for the SRAM latch storage element 300 described herein.
DC balance control element 320 comprises complementary data input terminals 324 and 326 which are coupled respectively to data output terminals (SPOS) 308 and (SNEG) 310 of storage element 300. DC balance control element 320 also comprises a first voltage supply terminal 328, and a second voltage supply terminal 330, which are coupled respectively to the third voltage supply terminal (VSWA_P) 376, and the fourth voltage supply terminal (VSWA_N) 378 of voltage controller 384 (See FIG. 7). DC balance control element 320 further includes a third voltage supply terminal 332, and a fourth voltage supply terminal 334, which are coupled respectively to the fifth voltage supply terminal (VSWB_P) 380, and the sixth voltage supply terminal (VSWA_N) 382 of voltage controller 384. (See FIG. 7) DC balance control element 320 further comprises data output terminal 322 that is coupled to data input terminal 348 of inverter 340.
A full explanation of the operation of DC balance control element 320 is found in U.S. Pat. No. 7,443,374, in corrected FIG. 6, and the corresponding text at Col. 11, lines 32-51, as corrected. And in FIGS. 12A through 12F and the corresponding text at Col. 17, line 18, through Col. 18, line 9.
Inverter 340 includes first voltage supply terminal 342, and second voltage supply terminal 344, which are coupled respectively to first voltage supply terminal (V1) 372, and second voltage supply terminal (V0) 374 of voltage controller 384 of FIG. 7. Inverter 340 also comprises data input terminal 348 coupled to data output terminal 322 of DC balance control element 320, and pixel voltage output terminal (VPIX) 346 coupled to pixel mirror 354. Responsive to the voltage asserted on input terminal 348 inverter 340 asserts the correct voltage among V0 374 and V1 372 onto pixel mirror 354 through output terminal 346.
U.S. Pat. Nos. 6,005,558, 6,067,065, 7,379,043, 7,443,374, 7,468,717 and 8,040,311 disclose backplanes compatible with the modulation method of the present application. These patents are incorporated into the present application in their entirety by reference.
FIG. 7 depicts voltage and control logic for a display system 394 compatible with the modulation method of the present invention. Display system 394 comprises an array of pixel cells 305 comprising a plurality of rows and columns, voltage controller 384, a processing unit 388, memory unit 386, and transparent common electrode 392. Transparent common electrode 392 overlays the entire array of pixel cells 305. In a preferred embodiment, pixel cells 305 are formed on a silicon substrate or base material, and are overlaid with an array of pixel mirrors 354 (from FIG. 6), each single pixel mirror 354 forming a part of one of the pixel cells 305. Each pixel cell 305 comprises the circuit elements disclosed in FIG. 6. A substantially uniform layer of liquid crystal material is located in between the array of pixel mirrors 354 and the transparent common electrode 392. Transparent common electrode 392 is preferably formed by a transparent conductive material such as Indium Tin-Oxide (ITO) coated onto a glass substrate (not shown) as previously disclosed in FIG. 3, items 240 and 242. Memory 386 is a computer readable medium including programmed data and commands. Memory 386 is capable of directing processing unit 388 to implement various voltage modulation and other control schemes. Processing unit 388 receives data and commands from memory unit 386, via memory bus 387, provides internal voltage control signals, via voltage control bus 390, to voltage controller 384, and provides data control signals (i.e. image data into the pixel array) via data control bus 385. Voltage controller 384, memory unit 386, and processing unit 388 may be separate units or alternative may form part of a larger circuit assembly in a larger integrated circuit or circuit board assembly.
Responsive to control signals received from processing unit 388, via voltage control bus 390, voltage controller 384 provides predetermined voltages to each pixel cells 305 via a first voltage supply terminal (V1) 372, a second voltage supply terminal (V0) 374, a third (logic) voltage supply terminal (VSWA_P) 376, and a fourth (logic) voltage supply terminal (VSWA_N) 378, a fifth (logic) voltage supply terminal (VSWB_P) 380, and a sixth (logic) voltage supply terminal (VSWB_N) 382. Voltage controller 384 also supplies predetermined voltages VITO_L by voltage supply terminal 396 and VITO_H by voltage supply terminal 397 to ITO voltage multiplexer unit 399. Voltage multiplexer unit 399 selects between VITO_L and VITO_H based on control signals received from processing unit 388. Processing unit 388 controls the logic state of (logic) voltage supply terminals VSWA_P 376, VSWA_N 378, VSWB_P 380, and VSWB_N 382 in synchronization with switching of VITO 398 between VITO_L 397 and VITO_H 396. ITO voltage multiplex unit 399 delivers VITO to the transparent common electrode 392, by voltage supply terminal (VITO) 398. Each of the voltage supply terminals V1 372, V0 374, VSWA_P 376, VSWA_N 378, VSWB_P 380, and VSWB_N 382 in FIG. 7 are global signals, wherein each global terminal supplies the same voltage to each pixel cell 305 throughout the entire pixel array at any given instant in the operation of display system 394. In the case of VITO 398, a single voltage is applied to transparent common electrode 392.
FIG. 8A depicts the movement of digital data and digital control signals in a display system. Display system 400 comprises microdisplay controller 420, digital image data input terminal 433, DDR SDRAM memory 430, memory control interface 431, memory data interface 432, microdisplay 440 and various digital control and data lines (402, 404, 406, 408, 410) that connect microdisplay controller 420 to microdisplay 440. Although DDR SDRAM 430 is preferably a DDR memory with a double data rate interface, other memory devices known in the art may be used. Digital image data input terminal may receive data from a digital input such as HDMI or DVI, or may receive data from a format converter device operative to receive digital or analog image signal and convert and reformat those signals as is well known in the art.
Line 402 may comprise a plurality of complementary clock lines. The clock lines allow microdisplay 440 and microdisplay controller 420 to conduct a synchronized transfer of data over a plurality of parallel data transfer lines 410. In one embodiment data transfer lines 410 comprise 64 parallel data lines. In another embodiment data transfer lines 410 comprises 128 parallel data lines. Those of ordinary skill in the art will recognize that the number of parallel data lines may be an arbitrary number and that the maximum number may be dictated by external factors such as the minimum spacing and minimum size of wire bond pads and the space available in which to fabricate said wire bond pads. Line 404 may comprise a set of operation code lines that control the microdisplay and instruct it to handle the data coming over parallel data transfer lines as address information or data information or as some other form of information that may be useful in a practical system. Line 406 may comprise a serial input-output interface. A serial input-output interface may be utilized to transfer control instructions from microdisplay controller 420 to microdisplay 440. Other control functions comprise functions to control other features of microdisplay 440 such as setup configuration. Line 408 may comprise additional features such as control of a temperature measurement sensor (not shown) with bidirectional data flow. A temperature sensor of the type required is disclosed in published patent application Ser. No. 10/627,230 (abandoned), the contents whereof are incorporated into the present application by reference. Other data lines may include such items as a field-invert (FI) signal (not shown) wherein the field-invert signal controls circuitry that triggers a change to the DC balance state of a pixel such as that shown in FIG. 6 by controlling DC balance control element 320 as previously described. Those of ordinary skill in the art will recognize other useful features that may be implemented in an interface between a microdisplay and a microdisplay controller. Therefore, the present list is not considered limiting.
FIG. 8B depicts a functional schematic of microdisplay controller 420. Digital data of an image to be displayed is received by terminal 433 on HDMI (High Definition Multimedia Interface) Interface 421. Alternatively, the digital data may be received from any industry standard or proprietary digital image interface. The digital data may be received from another device capable of rescaling images or enacting frame rate change or other changes or combination of changes. HDMI interface 422 receives the incoming digital data from a digital video source comprising a pixel clock, horizontal and vertical sync signals, and pixel data for one or more colors. Bit depth may be an industry standard such as 8 bits per color or another arbitrary or emerging standard.
Data received is transferred by logical/serial interface 429 to color shading correction unit 422. Color shading correction unit 422 receives digital image data and acts upon that data to apply correction factors to the image data such that the hue of the final display image is close to the desired color. The origins of color shading errors may originate in a number of causes, including non-uniformities in the display device. A more detailed explanation of color shading correction is found in U.S. Pat. Nos. 7,129,920 and 7,990,353, the contents whereof are incorporated into the present patent application by reference. In one embodiment the output data upon which color shading correction unit 422 has acted has different bit depth to that of the input data.
Color shading correction unit 422 delivers its output data to look-up table (LUT) unit 423 through logical/serial interface 434. LUT unit 423 acts upon the input data to apply a set of corrections for liquid crystal non-linearity and for other desirable corrections such as for gamma correction, thereby assuring that changes in the image data result in the expected change in the luminance of the image when displayed.
LUT unit 423 delivers its output data to byte-explode unit 424 via logical/serial interface 435. Byte-explode unit 424 acts upon data received from LUT unit 423 to convert said data into a form suitable for display. Byte-explode unit 424 takes the data and expands the number of bits comprising the data. In one embodiment byte-explode unit 424 maps the binary data to a larger number of binary weighted and non-binary weighted bits. In one embodiment the non-binary weighted bits comprise a set of “thermometer” or unary (Base 1) bits of higher order than the set of binary weighted bits. In one embodiment at least one of the unary bits is of different temporal weighting than the other unary bits. In one embodiment the temporal ordering of the unary bits differs from the order in which the unary bits are activated with increasing gray scale.
The expanded byte count data output of Byte-Explode unit 424 is transferred over logical interface 436 to DDR SDRAM Controller/Interface 425 for transfer to DDR SDRAM 430 (not shown) over memory data interface 432 for buffering. Placement and retrieval of the transferred data is responsive to instructions sent over memory control interface 431. In one embodiment the expand byte count data for a row is stored according the temporal order in which the data is to be displayed.
The expanded byte count data remains in DDR SDRAM 430 until retrieved by DDR SDRAM controller/Interface 425 over logical interface 432. DDR SDRAM Memory Controller/Interface 425 delivers the retrieved data over logical interface 437 to Bit Plane Scheduler and Sequencer 426.
Bit Plane Scheduler and Sequencer 426 receives expanded byte count data and converts the data into a time ordered sequence of row write events A row write event is the writing of an entire row of the display with binary data corresponding to a modulation state for each pixel on the row. In one embodiment the binary data is preceded by data defining the row to which the subsequent data is to be written. The time ordered sequence of row write events is delivered to microdisplay buffer and interface 427 by logical interface 438.
Microdisplay buffer and interface 427 performs actions such as voltage scaling to the signals representing the data for the row write actions to enable it to be electrically transferred to microdisplay 440 over output interface 439. Output interface 439 may be preferably a flexible printed circuit assembly (FPCA) or alternatively may form part of the same printed circuit board as the other components of microdisplay controller 420 or some other form as is known in the art. Output interface 439 comprises a set of parallel lines configured so as to enable the transfer of the row write information to microdisplay 440.
FIG. 8C depicts a functional diagram of the data transfer sections of microdisplay 440. Microdisplay comprises pixel array 441, left row decoder 445, right row decoder 446, column data register array 444, control block 443, and wire bond pad block 442. Wire bond pad block 442 is configured so as to enable contact with an FPCA or other suitable connecting means so as to receive data and control signals over lines from microdisplay controller 420. The data and control signal lines comprise compromise clock signal line 402, op code signal lines 404, serial input-output signal lines 406, bidirectional temperature signal lines 408, and parallel data signal lines 410.
Wire bond pad block 442 receives image data and control signals and moves these signals to control block 443. Control block 443 receives the image data and routes the image data to column data register array 444. Row address information is routed to row decoder left 445 and to row decoder right 446. In one embodiment the value of Op Code line 404 determines whether data received on parallel data signal lines 410 is address information or image data. In one embodiment the row address information acts as header, appearing first in time, to be followed by data for that row.
Row decoder left 445 and row decoder right 446 are configured so as to pull the word line for the decoded row high so that data for that row may be transferred from column data register array 444 to the storage elements resident in the pixel cells of that row of pixel array 441, as previously described in FIG. 6 and associated text.
Digital pulse width modulated displays offer several advantages over analog driven displays. First, it is possible to control time more precisely than voltage. Second, the pixel voltage can be constantly supplied and does not rely upon a capacitive element in the pixel to hold the charge. Third, it is less prone to be affected by high light loads. Prior art scrolling color systems have used analog pixels with one exception. Texas Instruments developed a scrolling color projector based on a multicolor spiral color wheel and a digital micromirror device (DMD). The Texas Instruments DMD uses pulse width modulation as described in U.S. Pat. No. 6,897,019 but does not use line by line row addressing as disclosed in the present application. Rather the DMD display is divided into groups of rows in which all rows in a group are written with that group in an off state and afterwards the modulation is applied to that group of rows. Applicant has developed hardware and software to enable application of its pulse width modulated spatial light modulators to the task of pulse width modulating a scrolling color display.